Curriculum Mapping

Suggested pacing

2 class sessions of 80 minutes each, or 4 sessions of 40 minutes

Syllabus references

• SPM Physics Form 5 — Chapter 5: Electronics (5.1 Semiconductors)

  Students explain the properties of semiconductor materials and distinguish between intrinsic and extrinsic semiconductors.

• SPM Physics Form 5 — Chapter 5: Electronics (5.2 Doping)

  Students describe the doping process for N-type and P-type semiconductors and identify charge carriers.

Key concepts

• Semiconductor properties and conductivity
• Energy band theory (valence band, conduction band, band gap)
• N-type and P-type doping mechanisms
• Charge carriers (electrons and holes) and majority/minority carriers

Common misconceptions

• Students often confuse "holes" with physical vacancies — clarify that holes behave as positive charge carriers
• Many students think doping adds electrical charge — emphasise that doped materials remain electrically neutral
• Students may conflate conductivity with the number of free electrons only, ignoring hole mobility

Suggested activities

• Use the Semiconductor Doping Simulator to show how doping concentration changes conductivity
• Group activity: classify common materials (silicon, germanium, copper, rubber) by band gap
• Discussion: why do modern devices use silicon rather than germanium?

Suggested pacing

3 class sessions of 80 minutes each, or 6 sessions of 40 minutes

Syllabus references

• SPM Physics Form 5 — Chapter 5: Electronics (5.3 Diodes)

  Students explain the operation of semiconductor diodes in forward and reverse bias, and describe rectification circuits.

Key concepts

• P-N junction formation, depletion region, and built-in potential
• Forward and reverse bias operation
• Diode I-V characteristics and the Shockley equation
• Half-wave and full-wave rectification
• Zener diodes and voltage regulation

Common misconceptions

• Students often assume diodes completely block reverse current — explain reverse saturation current and breakdown
• The "0.7V drop" shortcut causes confusion; reinforce that it is an approximation valid only at a specific operating point
• Students confuse Zener breakdown (controlled, designed) with avalanche breakdown (potentially destructive)

Suggested activities

• Live demo: use the Diode I-V Simulator to plot the characteristic curve and identify the knee voltage
• Circuit exercise: design a half-wave rectifier and observe the output with the simulator
• Compare: ideal diode model vs. constant voltage drop model vs. Shockley model

Suggested pacing

3–4 class sessions of 80 minutes each, or 7 sessions of 40 minutes

Syllabus references

• SPM Physics Form 5 — Chapter 5: Electronics (5.4 Transistors)

  Students describe the structure and operation of NPN and PNP BJTs, including common emitter configuration, current gain, and switching/amplification applications.

Key concepts

• BJT structure (NPN/PNP) and terminal naming (emitter, base, collector)
• Operating regions: cutoff, active, and saturation
• Current gain (hFE / β) and biasing techniques
• Common emitter, common base, and common collector configurations
• BJT as a switch and as a small-signal amplifier
• MOSFET structure (enhancement and depletion modes) and comparison with BJT

Common misconceptions

• Students confuse BJT (current-controlled) with MOSFET (voltage-controlled) — use the simulator to demonstrate this difference directly
• Many assume β is a fixed constant; show how it varies with IC and temperature using the simulator
• Students often think the transistor "creates" power in amplification — clarify that it controls power from the supply

Suggested activities

• Simulator demo: drive a BJT from cutoff through active to saturation — observe IC vs. VCE curves
• Design challenge: bias a common emitter amplifier for a given voltage gain using the interactive simulator
• Comparison exercise: BJT vs. MOSFET — when would you choose each for a given application?

Suggested pacing

3–4 class sessions of 80 minutes each, or 7 sessions of 40 minutes

Syllabus references

• Polytechnic Diploma EE — Analogue Electronics: Amplifier Theory and Small-Signal Analysis

  Students analyse amplifier circuits using small-signal models and calculate voltage gain, input/output impedance, and frequency response.

Key concepts

• Small-signal BJT and MOSFET models (hybrid-π and T models)
• Single-stage amplifier analysis (voltage gain, input/output impedance)
• Common emitter, common source, emitter follower, and source follower configurations
• Frequency response and bandwidth: Bode plots, Miller effect, dominant pole
• Multistage amplifier design and cascade analysis

Common misconceptions

• Students often confuse the DC biasing circuit with the AC small-signal circuit — draw them separately before combining
• The Miller effect on input capacitance is frequently underestimated; demonstrate how it drastically reduces bandwidth
• Students assume more stages always mean more bandwidth — show how cascading reduces the overall bandwidth

Suggested activities

• Small-signal analysis workshop: given a biased BJT circuit, derive the AC equivalent and calculate voltage gain
• Bode plot exercise: simulate the frequency response of a common emitter amplifier and identify the dominant pole
• Design challenge: cascade two amplifier stages to achieve a target voltage gain of 100 V/V

Suggested pacing

4 class sessions of 80 minutes each, or 8 sessions of 40 minutes

Syllabus references

• Polytechnic Diploma EE — Analogue Electronics: Operational Amplifiers and Applications

  Students analyse op-amp circuits in inverting, non-inverting, and differential configurations, and design active filters, integrators, and comparators.

Key concepts

• Ideal op-amp assumptions (infinite open-loop gain, zero input current, zero output impedance)
• Virtual ground principle and negative feedback analysis
• Inverting and non-inverting amplifier configurations and gain calculation
• Differential amplifier, summing amplifier, integrator, and differentiator
• Active filters (low-pass, high-pass, band-pass) and cutoff frequency design
• Comparators and Schmitt triggers (hysteresis)

Common misconceptions

• Students apply ideal op-amp analysis outside its valid region (e.g., near saturation) — always verify with simulation
• Virtual ground concept is frequently misunderstood as a real ground connection — emphasise it is a consequence of negative feedback
• Students confuse the open-loop gain (very high) with closed-loop gain (set by feedback resistors)

Suggested activities

• Interactive simulator: build an inverting summing amplifier and verify output using virtual ground principle
• Design a second-order active low-pass Butterworth filter for a given cutoff frequency
• Observation exercise: show how a comparator becomes a Schmitt trigger with positive feedback added

Suggested pacing

3 class sessions of 80 minutes each, or 6 sessions of 40 minutes

Syllabus references

• Polytechnic Diploma EE — DET: Digital Electronics — Logic Gates and Boolean Algebra

  Students distinguish between digital and analog signals, implement logic functions using fundamental gates, and verify truth tables.

• Community College Electronics Engineering — Introduction to Digital Systems

  Students apply Boolean algebra and DeMorgan's theorem to simplify logic expressions and implement them using standard gate families.

Key concepts

• Digital vs. analog signals, binary representation, and logic levels
• Number systems (binary, octal, hexadecimal) and conversions
• Seven fundamental logic gates: AND, OR, NOT, NAND, NOR, XOR, XNOR
• Boolean algebra, DeMorgan's theorem, and algebraic simplification
• Universal gates: NAND-only and NOR-only implementations

Common misconceptions

• Students often confuse Boolean "+" (OR) with arithmetic addition — emphasise the context difference
• NAND/NOR universality is counterintuitive; use the simulator to build AND/OR from NAND gates to demonstrate
• Students assume XOR and XNOR are rare; highlight their prevalence in adders, parity checkers, and comparators

Suggested activities

• Logic gate truth table simulator: verify all 7 gate types and observe NAND/NOR universality
• Boolean simplification worksheet: simplify a 3-variable expression algebraically then verify with truth table
• Design challenge: implement a full-adder using only NAND gates

Suggested pacing

3–4 class sessions of 80 minutes each, or 7 sessions of 40 minutes

Syllabus references

• Polytechnic Diploma EE — DET: Digital Electronics — Combinational Logic Design

  Students design and minimise combinational logic circuits using Boolean algebra, Karnaugh maps, and standard building blocks including adders, multiplexers, decoders, and comparators.

Key concepts

• Canonical forms: sum-of-products (SOP) and product-of-sums (POS)
• Karnaugh map minimisation for 2, 3, and 4-variable functions
• Half-adder and full-adder; ripple-carry and look-ahead carry adders
• Multiplexers (MUX), demultiplexers (DEMUX), encoders, and decoders
• Binary comparators and code converters (BCD, Gray code)

Common misconceptions

• Karnaugh map grouping rules (must be power-of-2 groups; wrap-around allowed) are frequently violated — practice with the interactive K-map tool
• Students confuse multiplexers (data selector) with decoders (address decoder) — contrast their truth tables side by side
• Ripple-carry adder propagation delay is often underestimated — show how it grows linearly with bit width using timing simulation

Suggested activities

• Interactive K-map exercise: minimise a 4-variable Boolean function and verify with the logic simulator
• Build a 4-bit ripple-carry adder from full-adder components using the circuit simulator
• Design challenge: implement a 4-to-1 multiplexer using only 2-input NAND gates

Suggested pacing

4–5 class sessions of 80 minutes each, or 9 sessions of 40 minutes

Syllabus references

• Undergraduate EEE — Digital Systems: Sequential Logic Design (Latches, Flip-Flops, Registers, Counters, FSMs)

  Students analyse and design sequential circuits including SR/D/JK/T flip-flops, shift registers, synchronous counters, and finite state machines (Mealy and Moore models).

Key concepts

• SR and D latches (level-triggered) vs. flip-flops (edge-triggered)
• D, JK, and T flip-flop operation, excitation tables, and characteristic equations
• Registers and shift registers (SISO, SIPO, PISO, PIPO)
• Synchronous and asynchronous counters; modulo-N counter design
• Finite state machines: Mealy vs. Moore models, state diagrams, state transition tables
• Timing diagrams, setup/hold time, and clock skew

Common misconceptions

• Students confuse synchronous (clock-edge-triggered) with asynchronous (level-triggered) operation — the timing diagram visualiser clarifies this
• State machine next-state logic is often conflated with output logic; Mealy vs. Moore distinction requires careful explanation with examples
• Students assume all flip-flops respond to both rising and falling edges — demonstrate edge-triggering with the timing simulator

Suggested activities

• Trace a 3-bit synchronous counter through its sequence using the timing diagram simulator
• Design a Mealy FSM for a sequence detector and simulate its state transitions step by step
• Peer exercise: two groups design equivalent Mealy and Moore machines for the same problem, then compare outputs

Suggested pacing

4 class sessions of 80 minutes each, or 8 sessions of 40 minutes (content-dense module)

Syllabus references

• Undergraduate EEE — Mixed-Signal IC Design: Data Converters (ADC and DAC) and Sampling Theory

  Students design and analyse ADC and DAC circuits, apply the Nyquist-Shannon theorem, and analyse quantisation error in mixed-signal systems.

• Undergraduate EEE — Signals and Systems: Nyquist-Shannon Sampling Theorem

  Students apply the sampling theorem to determine minimum sampling rates and explain aliasing artefacts in both time and frequency domains.

Key concepts

• Nyquist-Shannon sampling theorem and aliasing
• Sample-and-hold circuits and aperture error
• Quantisation error, LSB, and signal-to-quantisation-noise ratio (SQNR)
• DAC architectures: binary-weighted resistor and R-2R ladder networks
• ADC architectures: flash (parallel) and successive approximation register (SAR)
• Round-trip signal chain analysis: ADC→digital processing→DAC

Common misconceptions

• Students assume sampling at exactly 2×fmax is sufficient — explain that oversampling is required in practice to allow for practical anti-aliasing filters
• Quantisation error is often treated as random noise — clarify that it is deterministic (periodic sawtooth pattern) at low amplitudes
• Students confuse converter resolution (bits) with accuracy (actual static linearity performance including INL/DNL errors)

Suggested activities

• Aliasing demonstration: use the sample-and-hold simulator to show aliasing at sub-Nyquist sampling rates
• DAC design comparison: implement both binary-weighted and R-2R ladder DACs for 4-bit input and compare linearity
• ADC comparison: simulate flash vs. SAR ADC for the same input signal and compare speed, power, and complexity trade-offs