Assessment Strategies

Formative strategies

• Concept checks after each lesson (intrinsic vs extrinsic, band theory, doping)
• Doping simulator exploration: adjust concentration and observe conductivity change
• Exit ticket: describe in one sentence why silicon is preferred over germanium

Summative approach

Module 1 quiz gates access to Module 2. For graded courses, weight the quiz at 10% of the module grade with the option to retake (best score counts).

Rubric criteria

• Correctly identifies semiconductor as having conductivity between conductors and insulators
• Explains N-type and P-type doping with correct majority carriers
• Applies band gap concept to classify materials as conductors, semiconductors, or insulators
• Understands that doped semiconductors remain electrically neutral

Formative strategies

• Diode I-V concept check: identify operating region from a given VD value
• Rectifier simulator: vary load resistance and observe ripple voltage change
• Whiteboard exercise: sketch the I-V curve of a Zener diode from memory

Summative approach

Module 2 quiz includes circuit analysis questions requiring numerical answers (current calculations). Consider assigning a supplementary circuit design task for graded assessment.

Rubric criteria

• Correctly explains depletion region formation and built-in potential (~0.7V for silicon)
• Applies the constant-voltage drop model (or Shockley equation) to calculate the diode operating point
• Designs a half-wave or full-wave rectifier with appropriate smoothing capacitor
• Distinguishes Zener voltage regulation from forward-bias rectification

Formative strategies

• BJT operating region check: given VBE and VCE, identify cutoff/active/saturation
• Simulator: vary IB and plot IC vs. VCE to generate the output characteristic family
• MOSFET vs. BJT comparison exercise at the end of the module

Summative approach

Module 3 quiz covers both BJT and MOSFET operation with Q-point biasing calculations. A design challenge (bias a given amplifier stage) works well as a practical lab assessment.

Rubric criteria

• Identifies BJT operating region given VBE and VCE values
• Calculates Q-point using voltage divider biasing network
• Explains why MOSFET is voltage-controlled and BJT is current-controlled
• Computes small-signal voltage gain for a common-emitter amplifier stage

Formative strategies

• Small-signal model check: given a BJT circuit with known bias, draw the AC equivalent and identify gm
• Frequency response exercise: use the simulator to find the upper -3 dB frequency and explain the limiting capacitance
• Exit ticket: explain in one paragraph why the common-emitter configuration has high voltage gain but inverts the signal

Summative approach

Module 4 quiz emphasises small-signal analysis and frequency response. Supplement with a design project requiring students to specify an amplifier for a given gain-bandwidth requirement.

Rubric criteria

• Correctly draws the small-signal equivalent circuit for a given BJT amplifier stage
• Calculates voltage gain and input/output impedance for common-emitter and common-collector configurations
• Identifies the dominant pole and explains how the Miller effect limits bandwidth in common-emitter stages
• Designs a two-stage cascade amplifier to achieve a specified voltage gain

Formative strategies

• Virtual ground check: explain why the inverting input of an ideal op-amp is at 0V in a closed-loop inverting circuit
• Filter design exercise: calculate R and C component values for a specified first-order low-pass active filter
• Comparator vs. Schmitt trigger: observe hysteresis in the simulator and explain its benefit for noisy signals

Summative approach

Module 5 quiz tests op-amp circuit analysis across multiple configurations. A design task (select and justify an op-amp configuration for a given signal processing requirement) is an effective summative assessment.

Rubric criteria

• Applies virtual ground principle correctly to analyse inverting amplifier configurations
• Calculates closed-loop gain for inverting, non-inverting, and summing amplifier configurations
• Determines the cutoff frequency of a first-order and second-order active filter
• Explains hysteresis in a Schmitt trigger and its purpose in noise-immune comparator applications

Formative strategies

• Logic gate truth table check: given an unfamiliar gate symbol, derive its truth table using Boolean analysis
• Boolean simplification exit ticket: simplify F = AB + AB' + A'B using Boolean algebra in 5 minutes
• NAND universality demo: build an AND gate and an OR gate using only 2-input NAND gates in the simulator

Summative approach

Module 6 quiz tests logic gate operation, Boolean algebra, and DeMorgan's theorem. Supplement with a circuit implementation exercise where students build a specified function using only NAND or NOR gates.

Rubric criteria

• Correctly derives truth tables for all 7 fundamental logic gate types
• Applies DeMorgan's theorem to convert NOR expressions to equivalent AND/OR forms
• Converts between binary, hexadecimal, and decimal number systems accurately
• Implements a specified Boolean function using only NAND or NOR gates (NAND/NOR universality)

Formative strategies

• K-map exit ticket: group a 4-variable function correctly in under 5 minutes
• Simulator: build a 4-bit ripple-carry adder and verify truth table with all 16 input combinations
• Peer review: swap K-map simplifications and check each other's groupings for correctness

Summative approach

Module 7 quiz tests combinational design from truth table specification through K-map minimisation to gate implementation. Supplement with a timed design problem for practical skills assessment.

Rubric criteria

• Groups K-map cells correctly using power-of-2 groups including wrap-around
• Derives the minimised SOP expression from a 4-variable K-map
• Designs a 4-bit ripple-carry adder from full-adder components and traces carry propagation
• Implements a 4-to-1 multiplexer using standard combinational logic

Formative strategies

• Flip-flop type comparison: given a timing diagram, identify which flip-flop type produced the output sequence
• Counter timing trace: use the simulator to step through a 3-bit synchronous counter and record the state sequence
• FSM design exercise: draw a state diagram for a traffic light controller before using the simulator to verify

Summative approach

Module 8 quiz emphasises sequential circuit analysis including state tables and timing constraints. Pair with a hardware lab (if available) where students implement an FSM on an FPGA or verify a counter on a breadboard.

Rubric criteria

• Distinguishes SR, D, JK, and T flip-flop operation from truth tables and excitation tables
• Derives next-state logic equations for a given FSM state diagram
• Identifies setup and hold time violations from a timing diagram
• Designs a modulo-6 synchronous counter using D flip-flops

Formative strategies

• Nyquist check: given a signal frequency, determine the minimum sampling rate and identify aliasing risk
• Quantisation error calculation: for a 4-bit ADC with Vref = 5V, calculate LSB size and maximum quantisation error
• Round-trip simulation: set an input frequency above Nyquist in the simulator and observe aliasing at the DAC output

Summative approach

Module 9 quiz tests sampling theory and converter analysis. A design project (specify and compare ADC/DAC architectures for a given application: audio, sensor measurement, or control) works well as a capstone task for degree-level students.

Rubric criteria

• States the Nyquist-Shannon theorem correctly and applies it to determine minimum sampling rate for a given signal
• Calculates LSB size and quantisation error (SQNR) for a given ADC resolution and reference voltage
• Compares flash and SAR ADC architectures in terms of conversion speed, hardware complexity, and power consumption
• Analyses the output of an R-2R ladder DAC for a given 4-bit digital input code